[Oberon] Moving oberon to RISCV?

[Andreas Pirklbauer]

    > I realize [Moving oberon to RISC[-]V] is a lot of work,    > but there's quite a bit of momentum for it.    > What would need to be done to port Oberon?
In essence, you would need to do two things:
1. Find a suitable hardware board that supports the   RISC-V instruction set architecture (http://riscv.org)   or use an emulator with RISC-V support   such as QEMU (http://github.com/riscv/riscv-qemu)
2. Change the code generator of the Oberon compiler   to generate instructions for the RISC-V CPU (see also   http://oberon.wikidot.com/oberon-linux-revival-olr)
If you want to port the entire Oberon system, you mayalso need to adapt some inner and outer core modules(e.g., Kernel, Display), depending on the HW you use.
It would set you back 1-3 months, assuming familiaritywith both the RISC-V processor architecture and theOberon compiler, in particular its code generator.
-ap


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