[Oberon] Porting S3 / V4 Oberon
andreas_pirklbauer at yahoo.com
Mon Jan 4 02:52:00 CET 2021
> >Add the small number of “Original Oberon-2” features such as LOOP, EXIT
> >and RETURN to the compiler just to *initially* speed up the porting effort of
> >V4. But *eventually* eliminate those constructs *on* the then-ported system.
> >The advantage would be that one would not need to also deal with porting
> >complex, nested LOOP statements initially, thereby reducing risk of errors..
> Sounds like a plan. A dream would be to have a V4 successor named V6
> replacing V4 under Windows and Linux, and also running on the FPGA.
An alternative approach would be to *first* rewrite V4 under V4 itself to "clean
it up", as you had suggested in a previous message, i.e. first eliminate LOOP,
EXIT and RETURN *under V4*, step by step, while keeping V4 running. Then
compile for FPGA (either on V4 using a cross-compiler or on the FPGA itself).
That way, one doesn’t need to amend the Oberon-07 compiler.
PS: Personally, I would be more interested in V4 für RISC-V, where
Extended Oberon also runs (but with no memory limitations).
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