[Oberon] Lola-2 vs Verilog (was: Module finalization - language construct or system call)

[Chris Burrows]

> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> Skulski, Wojciech
> Sent: Tuesday, 5 January 2021 6:08 AM
> To: ETH Oberon and related systems
> Subject: Re: [Oberon] [EXT] Module finalization - language construct
> or system call
> 
> Yes, I would like to develop practical applications. I am not
> adversarial to LOOPs and friends. It is infinitely better than
> Verilog which we cannot avoid in this project. I love LOOPs after
> looking at Verilog.  Any Oberon construct looks lovely after looking
> at the Verilog.
> 

Looking at the Verilog code is this project is like looking at the assembler
output from the Oberon compiler.

The FPGA configuration code is actually written in Wirth's 'Logic
Description Language' Lola-2. The Verilog code is the output after the Lola
code has been processed by the Lola compiler

The Lola compiler and the Lola definition of the RISC5 computer are here:

https://people.inf.ethz.ch/wirth/Lola/index.html

It is not quite as pretty as Oberon-07 source code but it is a distinct
improvement on the resulting Verilog code.

When I started Astrobe for RISC5 in 2013 I had originally planned 3 phases
for the implementation. Phase 3 included integrating the Lola compiler into
the Astrobe IDE so that you could run it on Windows. I just revisited that
plan. Inevitably it has changed along the way and the Lola compiler is now
included in the fourth of five phases. The god news is that everything that
appeared before it has now been done. I'm real busy doing some work for ARM
Oberon-07 users right now but when that is complete I'll revisit the Lola-2
plan,

Regards,
Chris

Chris Burrows
CFB Software
https://www.astrobe.com/RISC5