[Oberon] Lola-2 vs Verilog (was: Module finalization - language construct or system call)

Pablo Cayuela pablo.cayuela at gmail.com
Tue Jan 5 04:55:54 CET 2021

Dear Chris,

I can recall that Project Oberon 2013 appears before LoLa gets a revival by
Prof Wirth again.
In fact I have a communication archived in my emails on 1st of August of
2014 telling me about the soon release of his new LoLa compiler, and also
mentioning that he had a Ceres working!


*More or less by chance I found on my old Ceres, which had been put away
and not used since many years, the source programs for the Lola compiler. I
will have to update them (Oberon-07) and then will send them to you,
assuming that you are still interested. But still I did not find the DCD

The book referred is his Digital Circuit Design for Computer Science
Students: An Introductory Textbook.
And on 7th December of the same year he told me that Lola was updated
(until then original Lola was still in his page):


*I appreciate your reply and continuing interest in Lola. Please notice
recent updates of LSC and LSV. If you have a Spartan-3 board, you will only
need to construct a daughter board for the SD-card. If you use a "bigger"
board, you will have to interface with an SDRAM, which is not so easy.*"

In fact I mounted Project Oberon 2013 before the Lola update.

I've been always interested in Lola, but the first version did not have the
goal to be translated to an industrial HDL, but to map the Lola description
to a tree data structure to simulate it on Oberon System and then check it
against the tree extracted from a graphical connection design of components
of an old open FPGA (XC6000) with ETHZ EDA tools (Trianus and Hades).
The new Lola-2 was conceived, I guess, for translating to Verilog in order
to be implementable with current tools, and it has many changes and
simplifications from the original one. Both are more readable than
Verilog/VHDL in any case.

Best regards,
Prof Pablo Cayuela

On Mon, Jan 4, 2021 at 6:30 PM Chris Burrows <chris at cfbsoftware.com> wrote:

> > -----Original Message-----
> > From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> > Skulski, Wojciech
> > Sent: Tuesday, 5 January 2021 6:08 AM
> > To: ETH Oberon and related systems
> > Subject: Re: [Oberon] [EXT] Module finalization - language construct
> > or system call
> >
> > Yes, I would like to develop practical applications. I am not
> > adversarial to LOOPs and friends. It is infinitely better than
> > Verilog which we cannot avoid in this project. I love LOOPs after
> > looking at Verilog.  Any Oberon construct looks lovely after looking
> > at the Verilog.
> >
> Looking at the Verilog code is this project is like looking at the
> assembler
> output from the Oberon compiler.
> The FPGA configuration code is actually written in Wirth's 'Logic
> Description Language' Lola-2. The Verilog code is the output after the Lola
> code has been processed by the Lola compiler
> The Lola compiler and the Lola definition of the RISC5 computer are here:
> https://people.inf.ethz.ch/wirth/Lola/index.html
> It is not quite as pretty as Oberon-07 source code but it is a distinct
> improvement on the resulting Verilog code.
> When I started Astrobe for RISC5 in 2013 I had originally planned 3 phases
> for the implementation. Phase 3 included integrating the Lola compiler into
> the Astrobe IDE so that you could run it on Windows. I just revisited that
> plan. Inevitably it has changed along the way and the Lola compiler is now
> included in the fourth of five phases. The god news is that everything that
> appeared before it has now been done. I'm real busy doing some work for ARM
> Oberon-07 users right now but when that is complete I'll revisit the Lola-2
> plan,
> Regards,
> Chris
> Chris Burrows
> CFB Software
> https://www.astrobe.com/RISC5
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
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