[Oberon] Project Oberon on current 'off-the-shelf' hardware
pablo.cayuela at gmail.com
Wed May 26 22:02:47 CEST 2021
Thank you again Chris.
I did not have the needed Pmods, I will build them, I hope some days from
now, because buying them and waiting for them will be eternal with my
country's conditions for both the pandemics (we are in a new lockdown) and
customs policy (always blocking personal off-shore buyings).
Prof Pablo Cayuela
On Tue, May 25, 2021 at 11:38 PM Chris Burrows <cfbsoftware at gmail.com>
> On Wed, May 26, 2021 at 5:21 AM Pablo Cayuela <pablo.cayuela at gmail.com>
> > I have the Nexys 4 with Cell RAM, not the DDR version that was renamed
> A7; all 3 has the same FPGA, but the one I have did not have the same pin
> assignment for peripherals on the constraint file.
> > I'm working in order to remap the Verilog original files from you to my
> > If you have any suggestions I'll check here on the list or in some days
> I will try the forum.
> > Thank you Chris for your great effort porting Oberon to these new boards.
> > Prof Pablo Cayuela
> > Argentina
> Digilent's documentation for both these boards is as excellent as
> usual which simplifies tasks like this. As far as I can see the pin
> assignments for the SD Card, VGA, USB HID and USB-RS232 peripherals
> are identical for both boards. The Switches, LEDs, Pushbuttons and
> Pmods JB and JC are all that need to be reassigned.
> I've now completed the remapping myself and will email you a
> constraints (XDC) file suitable for the Nexys 4 Rev B. I do not have
> that older board to test it myself so you should compare the mapping
> with your attempts so far and double-check it against the schematic
> before you proceed to generate a new bitstream file. You should be
> able to use all of the Project Oberon Workstation Verilog files that I
> provide for the Nexys A7-100T unchanged.
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
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