[Oberon] Re (2): Accessibility of FPGA configuration to V5 system.
arnim at actrix.gen.nz
Sat Jul 24 17:55:55 CEST 2021
The fact that LOLA outputs only Verilog is a limitation in the context of most FPGA vendors' software tools to convert to a bitstream, but in the past year QuickLogic has changed that game by going completely open source with their FPGA development tools, so that bitstream generation could change from the proprietary model, if someone makes that effort.
On Sat, 24 Jul 2021 08:17:09 -0700
peter at easthope.ca wrote:
> From: Michael Schierl <schierlm at gmx.de>
> Date: Sat, 24 Jul 2021 15:21:45 +0200
> > The V5 system treats the RISC5 processor as a black box. It is not
> > aware whether it is implemented as FPGA, as an ASIC or an emulator.
> Understood. Although obviously I would have to learn far more to
> re-implement on a new FPGA or to make another emulator and etc.
> > While there is LOLA, it will only output Verilog and there are no
> > tools in V5 to compile these to a bitstream of any FPGA model.
> A limitation of software implementation. (?)
> > Also, the processor does not expose any way of altering (parts of) the
> > bitstream it is running from.
> In other words, the host RISC machine can not change while the OS is
> At the fundamental level, a gate in the array is in one of two states.
> The state of a gate can't be switched while the system is running?
> How is that prevented?
> Thx, ... P.L.
> 48.7693 N 123.3053 W
> tel: +1 604 670 0140
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Arnim Littek <arnim at actrix.gen.nz>
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