[Oberon] [EXT] Re (2): Accessibility of FPGA configuration to V5 system.

Skulski, Wojciech skulski at pas.rochester.edu
Sat Jul 24 18:00:45 CEST 2021


>At the fundamental level, a gate in the array is in one of two states.
The state of a gate can't be switched while the system is running?
How is that prevented?

Some of your questions are probably answered on Wikipedia. More information is provided in P.P.Chu's books linked on RiskFive.com.



More information about the Oberon mailing list