[Oberon] Re (2): Accessibility of FPGA configuration to V5 system.
schierlm at gmx.de
Sat Jul 24 19:29:45 CEST 2021
Am 24.07.2021 um 17:17 schrieb peter at easthope.ca:
> From: Michael Schierl <schierlm at gmx.de>
> Date: Sat, 24 Jul 2021 15:21:45 +0200
>> The V5 system treats the RISC5 processor as a black box. It is not
>> aware whether it is implemented as FPGA, as an ASIC or an emulator.
> Understood. Although obviously I would have to learn far more to
> re-implement on a new FPGA or to make another emulator and etc.
>> While there is LOLA, it will only output Verilog and there are no
>> tools in V5 to compile these to a bitstream of any FPGA model.
> A limitation of software implementation. (?)
Mostly a limitation of not published bitstream formats for the major
>> Also, the processor does not expose any way of altering (parts of) the
>> bitstream it is running from.
> In other words, the host RISC machine can not change while the OS is
It would be possible to build a RISC machine that can change while the
OS is running. The current version does not provide that capability.
> At the fundamental level, a gate in the array is in one of two states.
> The state of a gate can't be switched while the system is running?
> How is that prevented?
From my limited understanding of how FPGA work (I took a one-semester
course about hardware design ~20 years ago when I was at university):
Initially the FPGA is usually programmed via JTAG interface. But the
JTAG interface is not exposed to the processor in the current design. It
is also possible (I believe in all FPGAs) to also expose (parts of the)
gates to be programmed from other (parts of the) gates, without going
though the JTAG interface, but that was not done in the Verilog files by
That is a bit like using EPROM (single E!) chips for firmware but not
providing any way to expose it to UV light, effectively making it a
one-time programmable ROM.
More information about the Oberon