[Oberon] Accessibility of FPGA configuration to V5 system.

Skulski, Wojciech skulski at pas.rochester.edu
Sat Jul 24 20:53:47 CEST 2021

> Michael Schierl [schierlm at gmx.de]
>> [LOLA] A limitation of software implementation.  (?)
> Mostly a limitation of not published bitstream formats for the major FPGA vendors.

More than that. The modern FPGAs provide "hardened IP cores" like DSP slices, SERDES elements with bitslip gears, or hard memory controllers for DDRx. These blocks have hundreds of documented tuning parameters, which combine into a semi-infinite numbers of combinations and interactions. I suspect there are many more hidden parameters than mentioned in the documentation. Publishing the format of the programming file would not provide knowledge "how to use the format and how to tune the parameters". In the vendor's tools tuning is done by the extensive logic of the place-and-route tools, various wizards, core generators, and the predefined soft cores. All of that must be replaced by the dreamed LOLA tool in order to not just output the bit file, but also properly place-and-route all the connections reflected in that file, plus all the needed analog tuning parameters.

Anyone who is airing such thoughts should first spend a couple weeks reading the official FPGA data sheets and User Guides for different aspects of the FPGA, followed by a few weeks of reading the vendors' fora, where the FPGA programmers report myriads of problems. Acquiring some background knowledge would prevent airing ideas which are manifestly oversimplified.

This discussion is akin to the previous discussion of running the OS on Rpi. Chris pointed out the vastly different ARM cores in various Rpis. Such a background knowledge is easy to acquire before posting. From my side I can advise trying BeagleBone Black or derivatives, where there is always the same ARM chip w/o variations. You do not have to deal with diverse ARM cores. But first consult the AM335x Technical Reference Manual counting about six thousand pages. Referring to the TRM could bring some better meaning to the propositions. 

>Initially the FPGA is usually programmed via JTAG interface. But the
>JTAG interface is not exposed to the processor in the current design. It
>is also possible (I believe in all FPGAs) to also expose (parts of the)
>gates to be programmed from other (parts of the) gates, without going
>though the JTAG interface, but that was not done in the Verilog files by
>NW either.

I would advise to stay away from "partial reconfiguration". If one wants to explore this topic then the User Guide is easy to find on the vendor's website. Read it first to know why you are advised to stay away. 


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