[Oberon] ALU 2015 and 2018

Paul Reed paulreed at paddedcell.com
Wed May 11 13:02:12 CEST 2022

Hi Wojtek,

You've got it - ignoring stalls, in RISC5 the only registers (in the HDL 
sense) which are updated on each clock cycle are the PC, the IR, and the 
flags. The value of every signal, once they all settle after propagation 
delays, is based off that set.

That also goes for the external memory, which is used combinatorially, 
ie asynchronously, as I've pointed out before. So the new instruction 
from the SRAM ends up being ready for the IR at the end of the cycle 

So I agree with Magnus - it's kind of not pipelined at all, really.

If you want to use memory with a synchronous interface, you'd have to 
figure out how to overcome that simple limitation of the design. I think 
it's a big ask of an intern! Even to drive in the direction of your 
goal, what would be the first step for him/her to aim to achieve?

RISC-V on the other hand was designed with pipelining and a synchronous 
memory interface in mind from the start.


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