[Oberon] ALU 2015 and 2018

[Skulski, Wojciech]

Hellwig:

> not very flattering, but true. :-)

My statement was meant as an alarm ;-(

>But I'm working on it. You can follow my efforts here:

I think that RISC5.v needs to be rewritten in both behavioral Verilog and VHDL. The value of this CPU is in the ISE rather than a particular way of coding. Clean and clear re-implementations will be very valuable for dusting off dark corners. The line count will go up. This would be an asset rather than a problem.

> The original design depends heavily on the assumption that
> the hardware synthesizer will set the initial state of all
> registers to zero.

In Xilinx devices the Global Reset will zero all the registers upon reloading the bit file. But how about soft reset w/o reloading the FW? Soft reset is needed in practice. 

> Simulating the architectural registers was easy; I found
> a Verilog description (from Xilinx) online.

Could you please post the pointer to "architectural registers"? What are these?

> Main memory (ISSI 256Kx16, 10 ns SRAM) isn't finished yet.

There is an entire chapter devoted to these chips  in "FPGA Prototyping...(Spartan-3 Version)" by P.P.Chu. He is discussing the timing and implementations of the memory controller for these chips. 

See https://academic.csuohio.edu/chu_p/rtl/fpga_vhdl.html and https://academic.csuohio.edu/chu_p/rtl/fpga_vlog.html

Note that RISC5top.v is using "clock gating" which is strongly discouraged by Chu because it is performed on regular routing fabric rather than the clock tree.  Namely, the statement below is generating the strobe using a gate, whose delay adds to the falling edge delay. The gate delay depends on the PVT and on the particular routing. If you need a precise timing then you would rather resynchronize with an FF.

assign SRwe = vidreq ? 1'b1: ~(wr & clk);

I am also not sure about the following assignment at the end of RISC5top.v. Is this clock routed on the global clocking net or regular fabric? The assignment looks simple, but it is rising some questions.

always @ (posedge clk50) clk <= ~clk;

Wojtek