[Oberon] ALU 2015 and 2018
hellwig.geisse at mni.thm.de
Fri May 13 18:10:30 CEST 2022
On Fr, 2022-05-13 at 14:40 +0000, Skulski, Wojciech wrote:
> In Xilinx devices the Global Reset will zero all the registers upon reloading the bit file. But
> how about soft reset w/o reloading the FW? Soft reset is needed in practice.
the signal for that is present, "rst" (it is active-low in fact).
It's rather easy to add a synchronous reset to all state elements.
> > Simulating the architectural registers was easy; I found
> > a Verilog description (from Xilinx) online.
> Could you please post the pointer to "architectural registers"? What are these?
These are the registers you can read/write from a program, by
instructions the processor is executing. They typically have
names such as R0...R15 in the corresponding assembler language
and are thus visible in the description of the ISA (instruction
set architecture). The set of architectural registers is often
named the "register file".
There are other registers (in the register-transfer language sense),
especially in pipelines, that are used to save any set of bits from
one clock cycle to the next. These are non-architectural registers,
because they don't show up in the description of the ISA. Examples
are the instruction register, or the pipeline registers.
Sorry, I don't have a pointer at hand.
> Note that RISC5top.v is using "clock gating" which is strongly discouraged by Chu because it is
> performed on regular routing fabric rather than the clock tree. Namely, the statement below is
> generating the strobe using a gate, whose delay adds to the falling edge delay. The gate delay
> depends on the PVT and on the particular routing. If you need a precise timing then you would
> rather resynchronize with an FF.
> assign SRwe = vidreq ? 1'b1: ~(wr & clk);
Yes, you can't normally do that, and it should be avoided. The
usual way around is using a clock with a rate two times the
original one, clocking a flip-flop in the standard way, and
using the output of the flip-flop for gating purposes.
> I am also not sure about the following assignment at the end of RISC5top.v. Is this clock routed
> on the global clocking net or regular fabric? The assignment looks simple, but it is rising some
> always @ (posedge clk50) clk <= ~clk;
You will have to use a "global clock buffer" to get clk onto
the clock tree in order to clock flip-flops with it - maybe
the synthesizer does insert one automatically. I don't know.
I for one would use a DCM (digital clock manager); all FPGAs
offer some variant of these. The statement above works for
simulation, though... :-)
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